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| Austin Semiconductor, Inc. AS8SF384K32 128K x 16 SRAM & PIN ASSIGNMENT (Top View) 512K x 16 FLASH SRAM / FLASH MEMORY ARRAY FEATURES * Operation with single 5V supply * High speed: 35ns SRAM, 90ns FLASH * Built in decoupling caps and multiple ground pins for low noise * Organized as 128K x 16 SRAM and 512K x 16 FLASH * Low power CMOS * TTL Compatible Inputs and Outputs * Both blocks of memory are user configurable as 256K x 8 NC A0 A1 A2 A3 A4 A5 FCS\1 GND FCS\2 SWE\1 A6 A7 A8 A9 A10 VCC SRAM & FLASH Mixed Module 68 Lead CQFP (QT) FLASH MEMORY FEATURES * * * * * * * Operation with single 5V (10%) Eight equal sectors of 64K bytes Any combination of sectors can be concurrently erased Supports full chip erase Embedded erase and program algorithms 20,000 program/erase cycles Hardware write protection SI/O 0 SI/O 1 SI/O 2 SI/O 3 SI/O 4 SI/O 5 SI/O 6 SI/O 7 GND SI/O 8 SI/O 9 SI/O 10 SI/O 11 SI/O 12 SI/O 13 SI/O 14 SI/O 15 NC NC A18 FWE\2 FWE\1 SWE\2 A17 SCS\2 OE\ SCS\1 A16 A15 A14 A13 A12 A11 VCC FI/O 0 FI/O 1 FI/O 2 FI/O 3 FI/O 4 FI/O 5 FI/O 6 FI/O 7 GND FI/O 8 FI/O 9 FI/O 10 FI/O 11 FI/O 12 FI/O 13 FI/O 14 FI/O 15 OPTIONS MARKINGS XT IT PIN A 0-18 PIN DESCRIPTION FUNCTION Address Inputs SRAM Data Input / Outputs FLASH Data Input / Outputs Output Enable SRAM Write Enables FLASH Write Enables SRAM Chip Selects FLASH Chip Selects Power Supply Ground No Connect * Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) * Timing SRAM 35ns SI/O 0-15 FI/O 0-15 OE\ SWE\ 1-2 FWE\ 1-2 FLASH 90ns -35 SCS\ 1-2 * Package Ceramic Quad Flatpack FCS\ 1-2 QT VCC GND NC GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS8SF384K32 is a 2 MEG CMOS SRAM and 8 MEG CMOS FLASH Module organized as 128K x 16 (SRAM) and 512K x 16 (FLASH). These devices achieve high speed access, low power consumption and high reliability by employing advanced CMOS memory technology. For more detailed information regarding the FLASH internal operations, programming, command definitions and functional descriptions, please see the AS8F512K32 data sheet located on our website at www.austinsemiconductor.com AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 Austin Semiconductor, Inc. FLASH 512K x 8 FCS\2 FEW\2 SRAM & FLASH Mixed Module AS8SF384K32 M3 M2 M1 / A0-A16 FI/O 8 - FI/O 15 SRAM 128K x 8 SCS\2 SWE\2 FLASH 512K x 8 FCS\1 FWE\1 FI/O 0 -FI/O 7 / A0-A16 SRAM 128K x 8 SCS\1 SWE\1 OE\ A0 - A18 M0 SI/O 8 - SI/O 15 SI/O 0 - SI/O 7 BLOCK DIAGRAM SRAM TRUTH TABLE MODE Read Write Standby OE\ L X X SCS\ L L H SWE\ H L X I\0 DOUT DIN High Z POWER Active Active Standby FLASH TRUTH TABLE OPERATION Read Output Disable Standby and Write Inhibit Write Sector Protect Verify Sector Protect Sector Unprotect Verify Sector Unprotect Erase Operations USER BUS OPERATIONS FCS\1-4 OE\ FWE\1-4 A0 A1 A6 A9 L L H X X X X L H H X X X X H X X X X X X L H L A0 A1 A6 A9 L VID L X X X VID L L H H H L VID see note 2 see note 2 L H H H see note 2 L L H H H H VID L H see note 1 see note 1 see note 1 see note 1 see note 1 I/O Data Out High Z High Z Data In X Data Out Data Out Data Out see note 1 LEGEND: L = VIL, H = VIH, X = Don't Care, VID = 12V, See DC Charateristics for voltage levels NOTE: 1. See Chip/Sector Erase Operation Timings and Alternate CE\ Controlled Write Operation Timings of AS8F512K32 data sheet. 2. See Chart 1 (pg. 6) of AS8F512K32 data sheet. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage of Vcc Supply Relative to Vss......................-.5V to +7V Storage Temperature............................................-65C to +150C Short Circuit Output Current(per I/O).................................20mA Voltage on Any Pin Relative to Vss....................-.5V to Vcc+1V Maximum Junction Temperature**...................................+150C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. PARAMETER Flash Data Retention Flash Endurance (write / erase cycles) 10 years 20,000 SRAM & FLASH Mixed Module AS8SF384K32 This is a stress rating only and functional operation on the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See the Application Information section at the end of this datasheet for more information. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < 125oC and -40oC to +85oC; Vcc = 5V +10%) SRAM SRAM PARAMETER Input High (Logic 1) Voltage Input Low (Logic 1) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Power Supply Operating Power Supply Current: Standby Current: CONDITION SYMBOL VIH VIL ILI ILO VOH VOL Vcc Icc MIN 2.2 -0.5 -10 -10 2.4 -4.5 MAX VCC +0.3 0.8 10 10 -0.4 5.5 325 UNITS V V NOTES 1 1, 2 OV < VIN < Vcc Output(s) disabled, OV < VOUT < Vcc IOH = -4.0 mA, Vcc = 4.5 IOL = 8.0 mA, Vcc = 4.5 SCS\ V V V mA 1 1 1 3 ISBT1 20 mA 3 1. All voltages referenced to VSS (GND). 2. -2V for pulse width <20ns. 3. ICC is dependent on output loading and cycle rates. The specified value applies with the outputs FLASH PARAMETER Vcc Active Current Vcc Active Current1, 2 Output Low Voltage Output High Voltage Output High Voltage Low VCC Lock Out Voltage CONDITION SYMBOL CE\ = VIL, OE\ = VIH, Vcc = Vcc ICC1 Max, f = 5MHz CE\ = VIL, OE\ = VIH, Vcc = Vcc Max, f = 5MHz IOL = 8mA, Vcc = Vcc Min IOH = -2.5mA, Vcc = Vcc Min IOH = -100m VCC = Vcc Min ICC2 VOL VOH1 VOH1 VLKO MIN ---0.85 x Vcc VCC-0.4 3.2 MAX UNITS NOTES 120 140 0.45 --mA mA V V V V NOTES: 1. Icc active while Embedded Program or Embedded Erase Algorithm is in progress. 2. Not 100% tested. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 Austin Semiconductor, Inc. CAPACITANCE (VIN = 0V, f = 1MHz, TA = 25oC)1 SYMBOL CADD COE CWE, CCS CIO PARAMETER A0 - A18 Capacitance OE\ Capacitance WE\ and CS\ Capacitance I/O 0- I/O 31 Capacitance SRAM & FLASH Mixed Module AS8SF384K32 MAX 50 50 20 20 UNITS pF pF pF pF NOTE: 1. This parameter is sampled. AC TEST CONDITIONS Test Specifications Input pulse levels.........................................VSS to 3V Input rise and fall times.........................................5ns Input timing reference levels...............................1.5V Output reference levels........................................1.5V Output load..............................................See Figure 1 IOL Current Source Device Under Test + + Vz = 1.5V (Bipolar Supply) Ceff = 50pf Current Source IOH NOTES: Vz is programmable from -2V to + 7V. IOL and IOH programmable from 0 to 16 mA. Vz is typically the midpoint of VOH and VOL. IOL and IOH are adjusted to simulate a typical resistive load circuit. Figure 1 AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 Austin Semiconductor, Inc. SRAM & FLASH Mixed Module AS8SF384K32 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (NOTE 5) (-55oC DESCRIPTION READ CYCLE READ cycle time Address access time Chip select access time Output hold from address change Output enable to output valid 1 Chip select to output in low Z 1 Output enable to output in low Z 1 Chip disable to output in high Z 1 Output disable to output in high Z SYMBOL RC AA t ACS t OH t AOE t LZCS t LZOE t HZCS t HZOE t t -35 UNITS MIN MAX 35 35 35 2 20 3 0 20 20 ns ns ns ns ns ns ns ns ns SRAM AC (SWE\ & SCS\ controlled) DESCRIPTION WRITE CYCLE WRITE cycle time Chip select to end of write Address valid to end of write Address setup time Address hold from end of write Data valid to end of write Data hold time WRITE pulse width 1 Output active from end of write 1 Write enable to output in High-Z 1. This parameter is guaranteed but not tested. SYMBOL WC CW t AW t AS t AH t DS t DH t WP1 t LZWE t HZWE t t -35 UNITS MIN MAX 35 25 25 0 0 20 0 25 2 20 ns ns ns ns ns ns ns ns ns ns AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 A0-A16 Austin Semiconductor, Inc. SRAM READ CYCLE NO. 1 tOH 431132121 24 41 3 5 435132121 14 41 2 3 431132121 24 43 5 tRC SI/O0-15 ADDRESS PREVIOUS DATA VALID SRAM READ CYCLE NO. 2 tAA tAA 665430 7 21 7543229 654321187654321 654329 210 7654329 665431187654321 210 754322187654321 654321187654321 210 0 7654329 654321187654321 2119 6543276 98 654321654321 7654326 987 765432154321 654321154321 987 754321154321 654321154321 987 7 7654316 6654326 982 tHZCS 2109876544321 5321 432 54321 2109876543211 321 2109876544321 54321 432 2109876554321 4321 2109876543211 876543211 432 876544321 5432 432 876543211 53211 876554321 44321 5321 432 876543211 SOE\ SCS\ t tLZCS ACS tAOE tLZOE 34 4311121 22 3 4331121 121 243 4331121 121 243 4311121 221 343 AS8SF384K32 Rev. 1.2 06/05 SI/O0-15 HIGH IMPEDANCE 6 tRC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. DATA VALID DATA VALID SRAM & FLASH Mixed Module tHZOE AS8SF384K32 654321 654321 654321 654321 A0-A16 Austin Semiconductor, Inc. SRAM WRITE CYCLE NO. 1 (Chip Select Controlled) t AW tCW 5432109 765430 765432987654321 543212187654321 21 21 7432101 565430187654321 6543 9 743212187654321 543212187654321 5654329 7 2109 tAH 8765434321 521 43 8765432121 5432 8765432121 34321 521 1 43 43 8765454321 54321 8765432121 SWE\ SCS\ tAS tHZWE t WP1 1 tWC tDS tLZWE tDH 43 4322 421 31 43211 43211 431 2 43211 4322 43 4311 2 1 4 1 4341210987654321 13 23 4311210987654321 2321098765432 4 SI/O0-15 A0-A16 SCS\ tAS WRITE CYCLE NO. 2 (Write Enable Controlled) t AW tCW t WP2 1 654320 543210 21 654320 543211987654321 654321987654321 543211987654321 654320 543211987654321 21 87654321 87654321 87654321 87654321 654321 654321 654321 654321 AS8SF384K32 Rev. 1.2 06/05 SI/O0-15 SWE\ tWC 7 DATA VALID DATA VALID Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. tDS tDH SRAM & FLASH Mixed Module tAH AS8SF384K32 Austin Semiconductor, Inc. SRAM & FLASH Mixed Module AS8SF384K32 FLASH ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (READ ONLY) (-55C < TA < 125C; VCC = 5V -5%/+10%) Parameter Symbol JEDEC Std. tAVAV tAVQV tELQV tGLQV tRC tACC tCE tOE tOEH tEHQZ tGHQZ tAXQX tHZ tDF tOH Speed Options Parameter Description Read Cycle Time (Note 3) Address to Output Delay Chip Enable Low to Output Valid Output Enable to Output Delay Read Toggle and Data\Polling Chip Enable High to Output High Z (Note 2, 3) Output Enable to Output High Z (Note 2,3) Output Hold Time from Addresses, CE\ or OE\, Whichever Occurs First Output Enable Hold Time (Note 3) Test Setup CE\=VIL, OE\=VIL CE\=VIL, OE\=VIL -35 Min Max Max Max Min Min Max 90 90 90 35 0 10 20 20 Min 0 Units ns ns ns ns ns ns ns ns ns NOTES: 1. See Test Specification for test conditions. 2. Output driver disable time. 3. Guaranteed but not Tested. Read Operation Timings Addresses t RC Addresses Stable ACC t t t FCS\ OE\ OEH CE t DF FWE\ Outputs OV High-Z t CE t OH High-Z Output Valid AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 Austin Semiconductor, Inc. SRAM & FLASH Mixed Module AS8SF384K32 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55C < TA < 125C; VCC = 5V +/- 10%) WRITE / ERASE / PROGRAM Erase and Program FWE\ Controlled Parameter Symbol JEDEC Std. tAVAV tWC tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tWHWH3 tVCHEL tAS tAH tDS tDH tOES tGHWL tCS tCH tWP tWPH Speed Options -90 90 0 45 45 0 0 0 0 0 45 20 300 15 120 50 11 Units ns ns ns ns ns ns ns ns ns ns ns us sec sec us sec Parameter Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Write Enable High to Input Transition Output Enable Setup Time Read Recover time Before Write (OE\ high to FWE\ low) FSC\ Setup Time FSC\ Hold Time Write Pulse Width Write Pulse Width High Min Min Min Min Min Min Min Min Min Min Min Min Max Max Min Max tWHWH1 Programming Operation tWHWH2 Sector Erase Operation tWHWH3 Chip Erase Operation VCC Setup Time Chip Program Time AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 Austin Semiconductor, Inc. Program Operation Timings WC 555h t t SRAM & FLASH Mixed Module AS8SF384K32 Addresses PA t AH FCS\ t GHWL t CH t OE\ t WP DS AOh t t WPH DH FWE\ t CS t FI/O0 - FI/O15 t PD VCS Vcc NOTE: PA= Program Address, PD= Program data, DOUT is the true data at the program address. AS8SF384K32 Rev. 1.2 06/05 10 543114321 2521 6 45 3 543132121 1321 2341 6 4143 543412121 2321 6 543112321 2541 4 652 AS PA PA WHWH1 Status DOUT Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. SRAM & FLASH Mixed Module AS8SF384K32 Chip/Sector Erase Operation Timings t Addresses 2AAh SA 555h for Chip Erase t AH FCS\ OE\ t GHWL t CH t t WP t FWE\ t CS DS 55h t WPH DH 30th 10 for Chip Erase t FI/O0 - FI/O7 or FI/O8 - FI/O15 Vcc t VCS NOTE: SA= Sector Address. VA = Valid Address for reading status data. AS8SF384K32 Rev. 1.2 06/05 11 543114321 2521 6 45 3 543132121 1321 2341 6 4143 543412121 2321 6 543112321 2541 4 652 WC t AS V A V A WHWH2 In Progress Complete Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Austin Semiconductor, Inc. SRAM & FLASH Mixed Module AS8SF384K32 Data Polling Timings (During Embedded Algorithms) t Addresses t V A ACC t CE t V A FCS\ t CH OE OE\ t OEH t DF FWE\ t OH Complement True Valid Data High-Z FI/O7 or FI/O15 FI/O0 - FI/O6 or FI/O8 - FI/O14 Complement Status Data Status Data NOTE: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Toggle Bit Timings ( During Embedded Algorithms) Addresses t V A ACC t CE t t V A FCS\ t CH OE OE\ OEH t DF FWE\ FI/O6 / FI/O2 or FI/O14 / FI/O10 t OH Valid Status Valid Status Valid Status Valid Status (first read) NOTE: VA=Valid address; not required for FI/O6 or FI/O14. Illustration shows first two status cycles after command sequence, last status read cycle, and array data read cycle. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 654321 654321 654321 654321 54541 323 21 11 5454321 321 21 11 5454321 32121 1 5432121 343 521 21 21 1 5454321 11 t RC 5432343 15 4 412121 543212121 15 3 2343 5 543112121 1343 4341 543212121 45 True 543454321 13 41 2321 543254321 11 2321 543232121 11 3 4541 543454321 1121 RC V A Valid Data High-Z V A V A Austin Semiconductor, Inc. SRAM & FLASH Mixed Module AS8SF384K32 MECHANICAL DEFINATIONS* Package Designator QT AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 Austin Semiconductor, Inc. SRAM & FLASH Mixed Module AS8SF384K32 ORDERING INFORMATION EXAMPLE's: AS8SF384K32QT-35/XT or AS8SF384K32QT-35/MIL Package Device Number Speed ns Type AS8SF384K32 QT -35 Process /* *AVAILABLE PROCESSES /IT = Industrial Temperature Range /XT = Extended Temperature Range /MIL = MIL-STD-883 para.1.2.2. NC -40oC to +85oC -55oC to +125oC -55oC to +125oC AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 |
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